Mohammad, Haidzir (2006) Design Of An 8 Bit Receiver Based On FPGA. Project Report. Universiti Sains Malaysia, Pusat Pengajian Kejuruteraan Elektrik dan Elektronik. (Submitted)
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Abstract
This project is developed in purpose to design and build a receiver in UART (Universal Asynchronous Receive Transmit) based on FPGA (Field Programmable Gate Array). There are two main parts associated in developing this receiver including software development and hardware installation. The most important part in this project is, in software development section where involving to develop the whole receiver application using Xilinx Foundation 2.1i software based on VHDL (Hardware Description Language) code via Behavioral Modelling. This receiver will have functionality as a receiver in UART to accept 8 bit data in serial and converted to 8 bit data in parallel for communication in computer system. For hardware installation part, it involve a whole connection circuitry with Xilinx XC4010PC84 demo board with computer via connection RS232 cable and the other hardware connection. The Xilinx XC4010PC84 demo board will act like a receiver and display the data that computer send in ASCII character and display it by LED in binary.
| Item Type: | Monograph (Project Report) |
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| Subjects: | T Technology T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering |
| Divisions: | Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Monograph |
| Depositing User: | Mr Engku Shahidil Engku Ab Rahman |
| Date Deposited: | 18 May 2023 08:24 |
| Last Modified: | 18 May 2023 08:24 |
| URI: | http://eprints.usm.my/id/eprint/58612 |
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