Bakar, Maya Abu (2015) Method For Validating The Integrity Of Clock Network Signal In Fpga Device. Masters thesis, Universiti Sains Malaysia.
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Item Type: | Thesis (Masters) |
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Additional Information: | Accession No: 875005937 |
Subjects: | T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK7800-8360 Electronics |
Divisions: | Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis |
Depositing User: | Mr Mohd Fadli Abd Rahman |
Date Deposited: | 24 Aug 2018 07:09 |
Last Modified: | 24 Aug 2018 07:09 |
URI: | http://eprints.usm.my/id/eprint/41500 |
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