Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application

Teng , Jin Chung (2014) Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application. Masters thesis, Universiti Sains Malaysia.

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Abstract

This report explain about the design of multiply-by-two amplifier for Analogue-To-Digital Converter. The specification of the operational amplifier is 40dB of gain, and 1MHz cut-off frequency. Silterra 0.13um process technology is used in this work. The amplifier topology used in this research is Folded cascode which gives larger output swing. Differential pairs Common-mode feedback is used to overcome the mismatch of source current and to fix the folded cascode output voltage level at 350mV. The proposed design was able to achieve DC gain of 44.77dB and 1.06MHz cut-off frequency. The designed amplifier power consumption is very low, which is 9.598mW. Figure of merit of this design are

Item Type:	Thesis (Masters)
Additional Information:	No Perolehan: 875006811
Subjects:	T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK7800-8360 Electronics
Divisions:	Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis
Depositing User:	Mr Mohd Fadli Abd Rahman
Date Deposited:	17 Jul 2018 08:36
Last Modified:	17 Jul 2018 08:37
URI:	http://eprints.usm.my/id/eprint/41078

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