A Monolithic 622MB/S Half Rate Clock And Data Recovery Circuit Utilizing A Novel Linear Phase Detector.

Chen, Hau Jiun and Azni Zulkifli, Tun Zainal and Abdul Aziz, Zulfiqar Ali and Mohd Noh, Norlaili (2004) A Monolithic 622MB/S Half Rate Clock And Data Recovery Circuit Utilizing A Novel Linear Phase Detector. In: Conference Proceedings : Analog And Digital Techniques In Electrical Engineering, 21-24 November 2004, Chiang Mai, Thailand .

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Abstract

Clock and data recovery (CDR) circuits are crucial components in high speed transceivers. In order to ensure synchronization between data and clock in the most economic way, clock information is embedded into the transmitted data stream.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Divisions: Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Conference or Workshop Item
Depositing User: Mr Erwan Roslan
Date Deposited: 06 Dec 2009 03:28
Last Modified: 20 Nov 2017 07:22
URI: http://eprints.usm.my/id/eprint/15178

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