High Resistivity Silicon- Deep-Level Doping Compensation Using Elemental Gold

Lew, Yit Shien (2017) High Resistivity Silicon- Deep-Level Doping Compensation Using Elemental Gold. Project Report. Universiti Sains Malaysia, Pusat Pengajian Kejuruteraan Elektrik & Elektronik. (Submitted)

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The rapid development of high speed devices increases the need for high resistivity substrate to improve noise isolation. The traditional method of using III-V semiconductor material for the substrate is associated with the problem of fabrication cost and complexity. Alternative solution such as silicon-on-insulator (SOI) has the thermal breakdown issue. Therefore, there is a need to produce high resistivity bulk substrate using silicon as a cheaper and less complex solution. Deep level doping compensation method using 3d transition element has been proposed to increase the bulk resistivity of p-type Czochralski silicon (CZ-Si) substrate. The purpose of this work is to investigate the potential of using transition elements as deep level dopants for n-type CZ-Si substrate. The enhancement of resistivity of n-type Si substrate provided by studied transition elements, i.e. gold (Au), silver (Ag), cobalt (Co), palladium (Pd), vanadium (V), manganese (Mn) and platinum (Pt) was determined and analyzed. The analysis on the resistivity plots of CZ-Si with background phosphorus concentration of 1014 cm-3 compensated using studied transition elements shows that Au and Ag are the best elements to be used as deep level dopants for n-type Si substrate. The highest theoretical resistivity enhancement provided by Au and Ag is about four order of magnitude, which is from 50 Ω-cm to 5x105 Ω-cm with Au or Ag concentration of 1015 cm-3. The use of Co and Pd are not desirable due to requirement of high solubility. V, Mn and Pt are disqualified as they do not provide compensation for n-type Si substrate. The significant difference between the results of theoretical calculation and measurement made onactual n-type Au-compensated CZ-Si wafer, which are 500 kΩ-cm and 80 kΩ-cm respectively, is due to the existence of inactive surface Au layer on Si wafer and slight difference in assumed position of Au deep levels in Si bandgap used in the calculation.

Item Type: Monograph (Project Report)
Subjects: T Technology
T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Divisions: Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Monograph
Depositing User: Mr Mohamed Yunus Mat Yusof
Date Deposited: 28 Jun 2022 04:03
Last Modified: 28 Jun 2022 04:03
URI: http://eprints.usm.my/id/eprint/53152

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