Lau, Jun Giap (2015) Self-Biased Folded Cascode Instrumentation Amplifier Using Chopper Technique For Ecg. Masters thesis, Universiti Sains Malaysia.
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Abstract
In twenty-first century, it has been witness the tremendous growth of technology in biomedical recording application particularly electrocardiogram (ECG) recording system and has had a profound impact on our daily life. The conventional ECG monitoring systems that are too bulky in nature which restrict the acquisition time has led to the design of low power battery operated portable ECG device. It helps to ensure good portability and enhanced mobility, freeing the patient from entanglement of wires which conceives annoyance and discomfort. In addition, the low frequency flicker noise (1/f) has been the biggest hindrance for reliable ECG monitoring application device since ECG signals have the characteristics of low amplitude and low frequency. Therefore, the goals of this work are to design a low power front end differential instrumentation amplifier for ECG monitoring device and to achieve low input referred noise of the amplifier specifically low frequency flicker noise. The circuit is based on the chopper technique which is implemented together with self-biased folded cascode structure that has significant lower power consumption than the predecessor’s approaches while keeping the performance unchanged. A self-biased scheme that saves power and reduces circuit area is chosen to eliminate the needs of external biasing circuitry by generating bias voltages from internal nodes of the circuit. It is developed through a series of iterative adjustments of component values and transistor sizes. For the case of chopper implementation, the usedmodulation technique converts the low frequency range of the input signals to a higher frequency range far above the dominant flicker noise. The second chopping module that acts as a demodulator brings the desired output back to the baseband and shifts the noise to the high chopping frequency. The modulated noise and the unwanted chopping spikes are then removed by a low frequency band pass filter. By the same token, folded cascode amplifier has benefit in low noise since smaller device size results in a better signal to noise ratio as the absolute area of the design contribute noises. The circuit is designed using SILTERRA 0.18 μm CMOS technology process with VIRTUOSO CADENCE. The pre-layout simulated results of the amplifier show ultra-low power of 1.926 μW and low noise of 415 nV/√Hz at 10 Hz which outperforms the renowned architectures of biomedical amplifier. Moreover, high differential voltage gain of 54.32 dB and 102.82 dB in CMRR are achieved.
| Item Type: | Thesis (Masters) |
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| Subjects: | T Technology T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering |
| Divisions: | Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis |
| Depositing User: | Mr Mohd Jasnizam Mohd Salleh |
| Date Deposited: | 12 Nov 2019 06:57 |
| Last Modified: | 22 Oct 2020 03:03 |
| URI: | http://eprints.usm.my/id/eprint/45778 |
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