Ng, Yit Ming (2018) Electrostatic Discharge Protection Circuit Design In Deep Sub-Micron Technology For Automotive Application. Masters thesis, Universiti Sains Malaysia.
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Abstract
Kebanyakan produk semikonduktor moden mudah terdedah kepada kerosakan nyahcas elektrostatik (ESD) dan ini menjadikan perlindungan ESD salah satu keperluan utama bagi litar bersepadu (IC). Walau bagaimanapun, spesifikasi ESD ketika ini menyebabkan kecerutan untuk mencapai tahap ESD yang lebih ketat terutamanya untuk segmen industri automotif berbanding dengan aplikasi lain. Aktiviti penskalaan agresif teknologi semikonduktor oksida logam gabungan (CMOS) terhadap rejim nanometer menjadikan IC mudah terdedah kepada kegagalan ESD dan pelaksanaan rangkaian perlindungan ESD akan menjadi lebih mencabar. Kajian ini bertujuan untuk membangunkan penyelesaian perlindungan ESD yang berkesan melalui metodologi reka-bentuk bersama prestasi litar. Dua kes ujian sebenar penambahbaikan ESD telah dikaji secara terperinci. Kajian ini menunjukkan bahawa isu LVDS ESD berkelajuan tinggi boleh diselesaikan dengan mengoptimumkan kedua-dua pemandu LVDS berkelajuan tinggi dan reka bentuk MOS ESD. Selain itu, kajian ini juga menunjukkan bahawa kekukuhan ESD yang rapuh dalam domain kuasa kecil boleh dipertingkatkan dengan memperkenalkan pengapit ESD novel. Pelaksanaan penambahbaikan ESD ini berjaya memenuhi kedua-dua spesifikasi ESD automotif yang ketat iaitu sebanyak 2000V bagi model badan manusia (HBM) dan 200V bagi model mesin (MM) dan membolehkan pengecilan CMOS yang berterusan. _______________________________________________________________________________________________________ Many modern semiconductor products are susceptible to the damage of electrostatic discharge (ESD) and this make ESD protection a must for integrated circuits. However, current ESD specifications cause a bottleneck for ESD qualifications especially for the automotive industry segment, which requires more stringent qualification requirements than other applications. The advancement of complementary metal-oxide-semiconductor (CMOS) transistors scaling into the nano-metric regime makes ICs more vulnerable to ESD failures and the implementation of an effective ESD protection designs become very difficult. This research aims to develop a robust ESD protection solution through circuit performance co-design methodologies. Two real test cases of ESD improvements have been studied in detail. This research has shown that the low voltage differential signaling (LVDS) ESD issue can be resolved by optimizing both the high-speed driver gate length and the ESD MOS design. In addition, it is also demonstrated that the fragile ESD robustness in small power domain can be enhanced by introducing a novel ESD clamp. By implementing these ESD improvements, the automotive ESD stringent requirements for both the 2000V human body model (HBM) and the 200V machine model (MM) could be met and enabled the continuation of CMOS scaling.
| Item Type: | Thesis (Masters) |
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| Uncontrolled Keywords: | Full text is available at http://irplus.eng.usm.my:8080/ir_plus/institutionalPublicationPublicView.action?institutionalItemId=4612 |
| Subjects: | T Technology T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK1001-1841 Production of electric energy or power. Powerplants. Central stations |
| Divisions: | Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis |
| Depositing User: | Mr Mohd Jasnizam Mohd Salleh |
| Date Deposited: | 06 May 2019 03:53 |
| Last Modified: | 06 May 2019 03:53 |
| URI: | http://eprints.usm.my/id/eprint/44278 |
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