Fpga-Based Accelerator for The Generation of Pseudo-Amino Acid Composition

Ching, Chee Chow (2015) Fpga-Based Accelerator for The Generation of Pseudo-Amino Acid Composition. Masters thesis, Universiti Sains Malaysia.

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Abstract

Pengurangan jurang antara bilangan protein baru yang belum dicirikan dan yang telah dikenali di dalam bank data protein telah muncul sebagai salah satu cabaran terbesar era pasca genomik. Permintaan kian meningkat untuk teknik-teknik yang dapat meramal ciri-ciri protein dengan cekap dan tepat berdasarkan maklumat urutan protein sahaja. Komposisi Asid Amino Pseudo (PseAAC) telah muncul sebagai teknik pemodelan yang berupaya menggabungkan maklumat urutan protein terpilih dalam model diskret. PseAAC telah digunakan secara meluas dalam ujikaji protein melalui pelbagai perisian penjana PseAAC. Oleh sebab penjanaan PseAAC lazimnya melibatkan pemprosesan data berskala besar, tempoh pemprosesan amat penting. Prospek untuk mengurangkan tempoh tersebut terhad kerana proses perisian lazimnya berjujukan. Maka, perkakasan yang boleh diaturcara seperti Field Programmable Gate Array (FPGA) muncul sebagai alternatif baru dengan keupayaan pemprosesan selari yang dapat mempercepat penghitungan PseAAC. Dalam penyelidikan ini, suatu pemecut berasaskan FPGA untuk penjanaan PseAAC telah diperkenalkan. Penjana tersebut terdiri daripada beberapa modul. Untuk mempercepat proses, dua modul yang paling intensif dalam penghitungan, iaitu Sum-of-Small-T dan T-u-minus-20, direka untuk pelaksanaan secara selari. Penjana tersebut direalisasikan melalui FPGA Altera Cyclone III. Proses berjaya dipercepat sehingga 31.5 kali ganda berbanding suatu penjana PseAAC berasaskan perisian Perl. Kesimpulannya, pengurangan tempoh penghitungan yang ketara telah dicapai melalui rekabentuk penjana PseAAC yang menggunakan kebolehan pemprosesan selari FPGA. ________________________________________________________________________________________________________________________ One of the biggest challenges in protein prediction post genomic age is narrowing the gap between the number of newly discovered and uncharacterized proteins and the number of known proteins in protein data banks. This leads to increased demand for efficient techniques to accurately predict protein attributes based solely on its sequence-order information. The Pseudo-Amino Acid Composition (PseAAC) is a modeling technique that incorporates, selectively, sequence-order information of a protein into a discrete model. PseAAC has been applied in numerous protein-related researches using various software-based PseAAC generators. Since this often involves large-scale data processing, computation time is of the essence. The prospect of further reducing computation time of the software is limited due to the sequential nature of software execution. Alternative platform such as programmable hardware has emerged as a solution to this bottleneck. Programmable hardware such as Field Programmable Gate Array (FPGA) enables parallel processing that speeds up computation of PseAAC. In this research, an FPGA-based PseAAC generator architecture is proposed. The architecture consists of several modules. To speed up computation, the two most computation-heavy modules of the architecture, the Sum-of-Small-T and T-u-minus-20, are designed to run in parallel. The generator is realized on the Altera Cyclone III FPGA and achieves computation speed increase of up to 31.5 times over a Perl-based PseAAC generator. In conclusion, significant computation speed improvement is achieved by designing the PseAAC generator to capitalize on the parallel processing capability of the FPGA.

Item Type: Thesis (Masters)
Additional Information: full text is available at http://irplus.eng.usm.my:8080/ir_plus/institutionalPublicationPublicView.action?institutionalItemId=1960
Subjects: T Technology
T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Divisions: Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis
Depositing User: Mr Mohd Jasnizam Mohd Salleh
Date Deposited: 06 Jun 2018 06:34
Last Modified: 06 Jun 2018 06:34
URI: http://eprints.usm.my/id/eprint/40702

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