Krishnan, Pragash Mayar (2015) Design And Simulation Of Low Power Comparator Using Dtts And Mtscstack Technques. Masters thesis, Universiti Sains Malaysia.
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Abstract
Permintaan untuk pembanding berkuasa rendah dan berkelajuan tinggi dalam penukar analog ke digital (ADC) sedang berkembang dengan pesat. Pembanding adalah blok yang penting dalam ADC. Penggunaan kuasa yang rendah telah menjadi perhatian utama teknologi terkini bagi alat-alat elektronik yang beroperasi pada kelajuan tinggi dengan pelbagai fungsi. Oleh yang demikian, keperluan semakin meningkat untuk peranti elektronik berkuasa rendah tanpa menjejaskan prestasinya. Dalam kajian ini, pembanding konvensional, pembanding dengan VDD rendah, pembanding dengan MTSCStack (Multi Threshold Super Cut of Stack) dan pembanding dengan DTTS (Dual Threshold Transistor Stacking) telah direka dan disimulasi dengan mengunakan teknologi 0.13 μm proses CMOS. Berdasarkan kajian ini, pembanding berkuasa rendah telah dicadangkan menggunakan gabungan teknik-teknik MTSCStack dan DTTS. Teknik MTSCStack mengurangkan kuasa kebocoran dalam mod aktif dan mengekalkan keadaan logik pada mod senyap. Manakala teknik DTSS bagi mengurangkan arus bocor tanpa memberi kesan kepada kelajuan. Di samping itu, jumlah penggunaan kuasa terutamanya kuasa dinamik telah dikurangkan pada jumlah yang besar melalui pengurangan VDD. Berdasarkan keputusan pasca susun atur, kuasa statik dan dinamik pembanding yang dicadangkan ialah 797 pW dan 17.55 μW. ________________________________________________________________________________________________________________________ The demand for high speed and low power comparator in Analog to Digital converter (ADC) is growing rapidly. Comparator is an important building block in ADC. Power consumption tends to be a major concern in today’s technology especially the electronic devices that are operating at high speed with multi functionality. Thus, the need is increasing for low power electronic devices without compromising its performance. In this study, conventional comparator, comparator with reduced VDD, comparator with MTSCStack (Multi Threshold Super Cut of Stack) and comparator with DTTS (Dual Threshold Transistor Stacking) have been designed and simulated in 0.13 μm CMOS process technology. Then, based on the study a low power comparator is proposed with MTSCStack and DTTS techniques. MTSCStack is proposed in order to decrease the leakage power in active mode and retaining the logic state of the comparator during the idle state. In other hand, DTSS is proposed to decrease the leakage current with less impact on the delay. In addition, the total power consumption especially dynamic power has been reduced by large amount by decreasing the VDD of the comparator. The static power and dynamic power of the post-layout proposed comparator is 797 pW and 17.55 μW respectively.
| Item Type: | Thesis (Masters) |
|---|---|
| Additional Information: | full text is available at http://irplus.eng.usm.my:8080/ir_plus/institutionalPublicationPublicView.action?institutionalItemId=1925 |
| Subjects: | T Technology T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK7868.D5 Digital electronics and Electronic circuit design |
| Divisions: | Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis |
| Depositing User: | Mr Mohd Jasnizam Mohd Salleh |
| Date Deposited: | 05 Jun 2018 04:21 |
| Last Modified: | 05 Jun 2018 04:21 |
| URI: | http://eprints.usm.my/id/eprint/40695 |
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