Krishnasamy, Raj Kumar
(2017)
Implementation Of Low Power Active Security.
Masters thesis, Universiti Sains Malaysia.
Abstract
Integrated Chip (IC) security has been a big concern for companies and consumers as the number of counterfeit devices have increased tremendously. Many counter-measures have been taken to improve the chip security like anti-tamper mesh, glitch protection and encryptions. The current anti tamper mesh usually runs on a single frequency and would consume a lot of power when the chip is idle. An inefficient mesh implementation would cause the die size to increase but the area protected would not be complete. This research will concentrate to make the anti-tamper mesh simple and secure yet, consumes low power. It uses the least resource in terms routing tracks and makes use of several operating frequencies to get the best of power consumption. The power number is compared using standard cell spice simulation numbers. The cells with reduced gate count and reduced frequency are compared with original settings using spice simulation number. The second experiment was done to compare the numbers from the spice simulations against power analysis tool. This is to ensure the spice simulation numbers reflect the power saving and to prove that the savings are real and can be even lower than estimated. Based on the experiments, it can be concluded that varying the frequencies of the active security mesh blocks and reduction of registers used can save power and still maintain the integrity of the active mesh. The spice simulation numbers are pessimistic and in power analysis, it is shown to be much lower. The total power saved by reducing the registers is 34.4%. When the registers and frequency are reduced, the total savings is about 96.6%.
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