Yuet, Cheryl She Siew
(2017)
Electrostatic Discharge For Sysyem On Chip Applications.
Masters thesis, Universiti Sains Malaysia.
Abstract
Integrated Circuit (IC) component level Electrostatic Discharge (ESD) requisites have stayed constant essentially for past two decades, having said so since the silicon technologies showing rapid advanced and efficacious control methods have prodigiously amended as well as improved. ESD standard JEDEC requirements has been part of success criteria on determine the ESD stress level in semiconductor industry. The standards applied across all product where its specification define for ESD test method, procedure, evaluation and classifying Human Body Model (HBM) a ESD model sensitive on component and ESD sensitivity to charge namely Charged Device Model (CDM). Apparently, the main gaps for this industrial standard missing of defining the withstand ESD stress voltage and recommended step test. Nevertheless, there is room of improvement to recommend guideline for when performing preliminary setup on pin combination for HBM test. In this thesis, will recommend a model change to more authentic but safe ESD stress target levels predicated on actual field data accumulated from 14nm and 22nm differences technology process devices as part of data for the learning on estimation the accuracy of the standards JEDEC JS001 and JS002 requirements on HBM and CDM respectively. Nonetheless, a much effective and time saving way established for data analysis of measurement leakage current increase before and after ESD test using JMP statistics tool on 14nm and 22nm small package devices. Driving to the standardization the new guideline for HBM successfully established. Lastly, the result of this research demonstrates the actual CDM test collected data on 14nm and 22nm more accurate on predicting the withstand voltage compare the peak current methodology.
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