Wang, Jian Zhong (2017) Clock Gating Assertion Check An Approach Towards Efficient Verification Closure On Clock Gating Functionality. Masters thesis, Universiti Sains Malaysia.
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Abstract
One of the power reduction techniques widely used in Register Transfer Level (RTL) stage of a design is clock gating. However, the addition of clock gating logics has increased the complexity of a design and therefore considerable amount of verification effort is required. The conventional verification method used widely is the scoreboard checking mechanism in Open Verification Methodology (OVM) verification environment. In addition, there are several methods proposed over the years to solve the verification of clock gating logics, for example, same master seed usage in multiple simulations, RTL to ACL2 translation and gated clock timing verification. However, the previous proposed methods still lack the capability to completely comprehend the checking of the correctness of clock gating logics of a design. The proposed verification method, called Clock Gating Assertion Check (CGAC) is aimed at addressing the limitation of the conventional verification method. The method is independent of verification environment used in a test bench. Besides, the proposed method is also aiming at achieving an efficient pre-silicon verification closure on clock gating logics with minimum verification effort. The proposed method is an automated flow that takes in two main inputs, namely codes written in Hardware Description Language (HDL) in RTL stage and clock domains information of a design. By using the main inputs, the proposed method generates assertion checks at possible clock gating boundary conditions. The clock gating logics of two Soft Intellectual Property (SIP) designs were verified using the CGAC method. The details of the implementation of the method are discussed in this thesis. By using the method, a total of five clock gating bugs were found and analysis on the impacts of the bugs is discussed. The proposed method further improved the efficiency of clock gating functional verification by 87.5% and 75% in terms of verification time spent in weeks for the first and second design respectively compared to the conventional method used which is OVM. However, there are a few limitations in the proposed method whereby it is used within Intel, the design information cannot be disclosed in this thesis and the designs are not within the author’s control. As a conclusion, based on the results obtained, it is concluded that the proposed method is proven effective in ensuring the correct clock gating implementation in a design.
| Item Type: | Thesis (Masters) |
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| Subjects: | T Technology T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering |
| Divisions: | Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis |
| Depositing User: | Mr Mohamed Yunus Mat Yusof |
| Date Deposited: | 09 Mar 2020 04:29 |
| Last Modified: | 17 Nov 2021 03:42 |
| URI: | http://eprints.usm.my/id/eprint/46474 |
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