Naif, Yasir Hashim
(2013)
Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits.
PhD thesis, Universiti Sains Malaysia.
Abstract
The most important limitation in planer MOSFETs is current leakage between the
source and the drain at the off-state (IOFF), which presents a critical problem in
securing circuit reliability. To mitigate this problem, there are new types of
transistors with a 3D structure, including silicon nanowire transistors (SiNWT). In
order to optimize dimensions, ambient temperature and orientation of channel in
SiNWT design, simulation is needed to characterize the behaviour of the SiNWT and
help making design decisions. Over the last decade, there have been many researches
focused on SiNWTs fabrication fields. However, these researches are all based on
fabrication fields. Therefore, in this research, dimensions, ambient temperature and
orientation of channel are modelled and taken into account to analyze performance
improvement of SiNWT. Furthermore, in order to optimize dimensions, and logiclevel
voltages of nanowire logic inverters circuits design, simulation is needed to
characterize the limits of noise margins of the NW logic inverter and help making
design decisions. There have been some proposed researches focused on NW logic
inverters fabrication without focusing on optimization of logic levels and dimensions
depending on noise margins as a limitation factor which represents a critical factor in
the working of logic circuits performance, and this study is intended to be the first
research to demonstrate dimensional optimization of nanowire logic inverter. This
research contains two main parts, first part on the characterization of silicon
nanowire transistor and the second on studying the characteristics of nanowire (NW)
inverters.
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