Teh, J-Me
(2013)
The Development Of A Capacitive Parasitic Element
Extraction And Estimation Methodology To Improve
Design Cycle.
Masters thesis, Universiti Sains Malaysia.
Abstract
In the chip industry today, the key goals of a chip development organization
is to develop and market chips within a short timeframe to gain foothold on market
share. Despite this requirement, chip design and manufacturing are increasing in
level of complexity due to advancement in process technology. Thus, the objective of
this research is to propose a design flow around the area of parasitic extraction to
improve the design cycle timeline. The proposed design flow utilizes the usage of
metal fill emulation as opposed to current flow which performs metal fill insertion
directly. By replacing metal fill structures with an emulation methodology in earlier
iterations of the design flow, this is targeted to help reduce runtime in fill insertion
stage. Design of experiments methodology utilizing RCBD, ANOVA and Fisher’s
LSD are used to select an appropriate emulated metal fill width to improve emulation
accuracy. The experiment is conducted on 45nm and 65nm process technologies and
test cases of different sizes, ranging from 1000 gates to 21000 gates to observe
differences exhibited in the outcome. When compared with the general design flow,
around 92% of all the nets in the design show differences of lesser than 15% in
capacitance value for 45nm and 88% for 65nm. This is in line with the permissible
error of a 2.5D parasitic extraction engine to achieve within 20% difference in
extracted capacitance values. Runtime reduction achieved was from 41% to 43%
lesser than the general design flow for the number of 15 iterations. In industrial usage,
this flow is appropriate for new designs where number of iterations required due to
design optimization is high.
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