Compact Modeling Of Deep Submicron CMOS Transistor With Shallow Trench Isolation Mechanical Stress Effect [TK7871.99.M44 T161 2008 f rb].

Abstract

Thesis ini memperkenalkan satu model padat, dua model berasaskan empirikal dan satu model berasaskan fizikal untuk kesan tekanan mekanikal Pengasingan Peparit Cetek (STI) ke atas transistor CMOS di bawah submikron. This thesis introduces a compact model, two empirical-based models and a physical-based model of Shallow Trench Isolation (STI) mechanical stress effect on deep submicron CMOS transistor.