Modelling And Analysis Of Stacked-Chip Scale Packages (S-Csps) Encapsulation Process Using Finite Difference Method [TK7874. K46 2007 f rb].

Abdullah, Muhammad Khalil (2006) Modelling And Analysis Of Stacked-Chip Scale Packages (S-Csps) Encapsulation Process Using Finite Difference Method [TK7874. K46 2007 f rb]. Masters thesis, Universiti Sains Malaysia.

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    Abstract

    Pada hari ini, peranti-peranti mikroelektronik menjadi lebih padat, ringan dan mempunyai lebih fungsi, ini termasuklah pakej skala cip-bertingkat (S-CSP). Ia adalah satu teknologi yang memberi opsyen kepadatan pempakejan yang tinggi. Nowadays, microelectronic devices become more compact, lighter in weight and more functional, including Stacked-Chip Scale Package (S-CSP). It is a technology which has high density packaging options.

    Item Type: Thesis (Masters)
    Subjects: T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK7885-7895 Computer engineering. Computer hardware
    Divisions: Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraan Mekanikal (School of Mechanical Engineering)
    Depositing User: Mr Erwan Roslan
    Date Deposited: 16 Apr 2009 10:01
    Last Modified: 13 Jul 2013 12:05
    URI: http://eprints.usm.my/id/eprint/9178

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