Mohd. Noh, Norlaili (1995) VLSI Implementation Of A Systolic Array Viterbi Decoder. Masters thesis, Universiti Sains Malaysia.
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Abstract
This project is on developing a Vi terbi decoder which uses the trace-back method structured in a systolic array fashion. It is believed that this architecture can reduce the size of the decoder as it minimizes the connections between component modules and requires a smaller storage space. The trace-back method can reduce the amount of hardware which is normally a problem with register exchange decoder. It is also suitable for achieving a higher speed of operation as tracking, updating and storage of the information sequence can be accomplished simultaneously during a single clock cycle.
| Item Type: | Thesis (Masters) |
|---|---|
| Subjects: | L Education > LC Special aspects of education > LC5800-5808 Distance education. |
| Divisions: | Pusat Pengajian Pendidikan Jarak Jauh (School of Distance Education) > Thesis |
| Depositing User: | Mr Aizat Asmawi Abdul Rahim |
| Date Deposited: | 18 Nov 2025 06:35 |
| Last Modified: | 18 Nov 2025 06:35 |
| URI: | http://eprints.usm.my/id/eprint/63228 |
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