Clock Gating Technique For Power Reduction In Digital Design

Khor, Peng Lim (2012) Clock Gating Technique For Power Reduction In Digital Design. Masters thesis, Universiti Sains Malaysia.

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Power reduction techniques become increasingly important to the deep sub-micron scale digital integrated circuit (IC) design. Multiple power reduction techniques are used to keep the power consumption under control even when the operating frequency is high. Same power reduction technique might not give the same power saving efficiency when the operating frequency increases. Power reduction effectiveness decreases follows downward of the design flow. For an IC design house without fabrication factory, levels of power optimization in the design flow are very limited.

Item Type: Thesis (Masters)
Subjects: T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Divisions: Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis
Depositing User: ASM Ab Shukor Mustapa
Date Deposited: 03 Jul 2019 00:58
Last Modified: 03 Jul 2019 00:58

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