Technique Of Pvt Analysis On Sd Controller Timing Validation For 28nm Soc Fpga

Yusni, Nur Amalina Aiza (2015) Technique Of Pvt Analysis On Sd Controller Timing Validation For 28nm Soc Fpga. Masters thesis, Universiti Sains Malaysia.

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SoC is a system on chip that consists of memory, processor and peripherals. Inside SoC there are many IP blocks such as secure digital (SD) controller block. As time fly, SoC has increase their demand in the industries. SD was widely used as the data store since it is compatible and have a large capacity. To remain the quality of the IP, beside functional validation, it is necessary to ensure the SD controller meet its timing specification. Typically, for protocol timing characterization it is difficult to adjust the timing as it needs to properly measure the input IO timing parameters (Tco,Tsu and Th). However, the problem is most tools do not adjust timing for measurement. Logic analyzers can only captures timing, but do not have the capabilities for user to adjust the timing. Full size ATE testers might be able adjust timing, but programming protocol aware test vectors takes many months of development per protocol. Additionally, ATEs cannot accommodate protocols with non-deterministic timing elements. To eliminate these problems, reduce characterization time, and improve timing related to IO protocol characterization, this thesis will introduce a new methodology using a configurable, high granularity, protocol aware delay element. The additional methodology that will be used in this project is using an additional timing delay board which consist of Max II device. The Max II device will have a delay design inside to provide delay to input clock. User can control the setting of the delay by changing the external selector pin on the timing delay board. The external pin is three bit setting from 000 to 111. Each of the setting will have a different delay path depends on the design in Max II. Using this methodology, an analysis on PVT has been conducted to get the worst case of the minimum setup time and hold time. To complete the timing datasheet for SD controller, output delay has been measure using command protocol. Based on the analysis, SS corner at Vmin and cold temperature condition gives the worst minimum setup time (2.56ns), minimum hold time (1.5ns) and output delay.

Item Type: Thesis (Masters)
Additional Information: Accession No: 875005924
Subjects: T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK7800-8360 Electronics
Divisions: Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis
Depositing User: Mr Mohd Fadli Abd Rahman
Date Deposited: 24 Aug 2018 02:27
Last Modified: 24 Aug 2018 02:27

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