Puan , Chia Kian
(2016)
Development Of Simple I3c Controller Bus Functional Modeling For Internal Test Card Verification.
Masters thesis, Universiti Sains Malaysia.
Abstract
Sensors usage are becoming broader as the technology gets more advance in recent years, with its features becoming more sophisticated and can be found in wide range of products from cellphone to Internet of Thing (IoT). As a result, demand for new interface with more speed and bandwidth to transfer more data from sensor to the system for processing and existing communication will soon be surplus to the requirement to be able to transfer the large data fast enough to be processed. Hence, Improved Inter-Integrated Circuit (I3C) is introduced by Mobile Industry Processor Interface Alliance (MIPI) as new interface standard that able to deliver the required performance compared to its predecessor I2C, at the same time maintain the low power operation mode that’s essential to the sensor subsystem. As part of a new interface readiness, an Intel in-house I3C Test Card will be used in validation activity against the Controller in place of actual sensors or devices. While there is not any I3C controller based system available for testing yet, there is a need to have a temporary solution to replicate it in to enable the said I3C Test Card in order to have it ready once a system with I3C controller is available for validation. Thus, an I3C BFM is proposed to enable simple I3C protocol cycle transfers between it and I3C Test Card to achieve just that. I3C BFM will be FPGA based and capable to perform Enter Dynamic Address Assignment (ENTDAA) flow. The flow will require BFM to issue I3C Broadcast CCC and Modal Broadcast CCC protocol cycles. I3C Test Card will be assigned with a dynamic address upon completion of the flow and it is ready to send or receive I3C transaction as a result.
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