Rajumanikam, R. Logeish Raj
(2015)
Reusable Automated Agent For Universal Verification Methodology System Testbench.
Masters thesis, Universiti Sains Malaysia.
Abstract
Pre-silicon verification process is an important cog in an application specific integrated chip design cycle. It is considered one of the biggest bottle-neck in modern day design projects. Thus, verification efficiency and productivity has gained a lot of attention lately and will be the driving factor of this research. The purpose of this research is to build a verification solution that actively promotes reusability and interoperability of verification components and improve the automation within the verification solution. These are identified as important concepts to improve verification efficiency and productivity. A state of the art UVM (Universal Verification Methodology) verification solution centered on these concepts is built for the sideband module of a hard memory controller. First, the verification requirements of the sideband module are investigated. Next, existing testbench solutions were evaluated for its reuse capabilities. This is followed by proposing and implementing a testbench architecture that highly reuses existing verification components and be reused friendly itself. Next, the architecture is improved to allow higher level of automation within the testbench. The implemented verification solution is then measured and analysed for its reusability and automation. The result obtained shows the implemented verification solution
achieves a reusability of 21.70% in a system level testbench and 49.67% in the standalone sideband verification environment. In addition, the autonomous agent approach implemented in the architecture reduces the test writer's burden by at least 60% and up to 78%.
Actions (login required)
 |
View Item |
![[img]](http://eprints.usm.my/style/images/fileicons/application_pdf.png)
