Mohamed Sultan, Fahmy Hafriz
(2015)
Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect.
Masters thesis, Universiti Sains Malaysia.
Abstract
This research highlights the development of test platform of FPGA interconnect to capture marginal open defect on Altera® Stratix V devices. The need for at-speed test
was due to the increasing number of marginal open defects, resulting from manufacturing process complexity anticipated from continuously shrinking transistors
towards nanometer (nm) scale. The defect was unable to be captured by current stuck-at test and this research utilized the Launch on Shift (LOS) transition delay method to detect the marginal open defects. Towards the final implementation, there are few unique design implemented in order to generate the at-speed clocks and the pipelined scan enable signals to support LOS method. Meanwhile, the ability to test the interconnect on at-speed frequency required new routing tool control variables to limit the interconnect path lengths and device power consumption. The control variables are
discussed further in this research. The LOS test patterns used in this research managed to cover up to 81% of the overall routing resources for marginal open defect effectively. Furthermore, the test was successfully implemented at frequencies up to 400 MHz and proven to be sensitive to routing delay to capture marginal open defects. The ability to capture the defect with only 0.56 kΩ resistance is better than the initial 3 kΩ target in
this research. It is also better than other literatures which targeted between 6 kΩ to 10 kΩ only.
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