A Test Vector Minimization Algorithm Based On Delta Debugging For Post-Silicon Validation Of Pcie Rootport

Toh , Yi Feng (2017) A Test Vector Minimization Algorithm Based On Delta Debugging For Post-Silicon Validation Of Pcie Rootport. Masters thesis, Universiti Sains Malaysia.

[img]
Preview
PDF - Submitted Version
Download (978Kb) | Preview

    Abstract

    In silicon hardware design, such as designing PCIe devices, design verification is an essential part of the design process, whereby the devices are subjected to a series of tests that verify the functionality. However, manual debugging is still widely used in post-silicon validation and is a major bottleneck in the validation process. The reason is a large number of tests vectors have to be analyzed, and this slows process down. To solve the problem, a test vector minimizer algorithm is proposed to eliminate redundant test vectors that do not contribute to reproduction of a test failure, hence, improving the debug throughput. The proposed methodology is inspired by the Delta Debugging algorithm which is has been used in automated software debugging but not in post-silicon hardware debugging. The minimizer operates on the principle of binary partitioning of the test vectors, and iteratively testing each subset (or complement of set) on a post-silicon System-Under-Test (SUT), to identify and eliminate redundant test vectors. Test results using test vector sets containing deliberately introduced erroneous test vectors show that the minimizer is able to isolate the erroneous test vectors. In test cases containing up to 10,000 test vectors, the minimizer requires about 16ns per test vector in the test case when only one erroneous test vector is present. In a test case with 1000 vectors including erroneous vectors, the same minimizer requires about 140μs per erroneous test vector that is injected. Thus, the minimizer’s CPU consumption is significantly smaller than the typical amount of time of a test running on SUT. The factors that significantly impact the performance of the algorithm are number of erroneous test vectors and distribution (spacing) of the erroneous vectors. The effect of total number of test vectors and position of the erroneous vectors are relatively minor compared to the other two. The minimization algorithm therefore was most effective for cases where there are only a few erroneous test vectors, with large number of test vectors in the set.

    Item Type: Thesis (Masters)
    Subjects: T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering
    Divisions: Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis
    Depositing User: Mr Mohd Fadli Abd Rahman
    Date Deposited: 13 Mar 2018 16:47
    Last Modified: 17 May 2018 11:10
    URI: http://eprints.usm.my/id/eprint/39524

    Actions (login required)

    View Item
    Share