Ramachandran, Nathan (2013) Design method to transmit and receive source synchronous signals using source asynchronous. Masters thesis, Universiti Sains Malaysia.
![[img]](http://eprints.usm.my/style/images/fileicons/application_pdf.png)
|
PDF
Download (248kB) | Preview |
Abstract
Field Programmable Gate Array (FPGA) yang berkos rendah menawarkan data dengan kelajuan terhad untuk saluran sumber segerak Low-Voltage Differential Signaling (LVDS) Input-Output (IO) tetapi kelajuan lebih tinggi untuk saluran sumber tidak segerak. Cyclone V adalah peranti berkos rendah yang menawarkan saluran LVDS IO yang menyokong kadar kelajuan 1.25 Gigabit sesaat (Gbps) tetapi saluran tidak segeraknya menyokong kadar kelajuan 5 Gbps. Secara umum, satu lagi had sumber sistem segerak adalah jarak penghantaran saluran jam perlu sependek yang mungkin untuk menghapuskan condong antara saluran data dan saluran jam. Maka, objektif kajian ini adalah membentangkan penyelesaian untuk menghantar dan menerima sumber isyarat segerak pada kelajuan yang lebih tinggi menggunakan saluran sumber tidak segerak yang terdapat dalam peranti FPGA. Penyelesaian yang dicadangkan juga akan membolehkan jarak penghantaran saluran jam yang lebih panjang digunakan. Lower cost Field Programmable Gate Array (FPGA) devices offer limited data rate speed for source synchronous Low-Voltage Differential Signaling (LVDS) Input-Output (IO) interfaces but higher data rate speeds for source asynchronous transceivers channels. Cyclone V which is a low cost FPGA device supports LVDS IO channels for data rates up-till 1.25 Gigabit per second (Gbps) meanwhile the transceiver channels support data rates up-till 5 Gbps. In general, another known limitation of source synchronous system is the clock transmission path need to be as short as possible to eliminate high skew between data channel and clock channel. Hence, this research objective is to presents a solution to transmit and receive source synchronous signals at higher data rates using the available source asynchronous channels in the FPGA devices. The solution will also address the limitation of clock transmission path length.
| Item Type: | Thesis (Masters) |
|---|---|
| Subjects: | T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK5105 Computer networks and Data transmission systems T Technology > TK Electrical Engineering. Electronics. Nuclear Engineering > TK7868.D5 Digital electronics and Electronic circuit design |
| Divisions: | Kampus Kejuruteraan (Engineering Campus) > Pusat Pengajian Kejuruteraaan Elektrik & Elektronik (School of Electrical & Electronic Engineering) > Thesis |
| Depositing User: | Mr Badli Syahar Bakhtier |
| Date Deposited: | 12 Apr 2017 01:48 |
| Last Modified: | 12 Apr 2019 05:26 |
| URI: | http://eprints.usm.my/id/eprint/33021 |
Actions (login required)
 |
View Item |
